1. Field of the Invention
The present invention relates to a packet switching system for use in a packet communication system and more particularly to a packet switching system which uses a single duplex bus.
2. Description of the Related Art
A conventional packet switching system uses two buses, i.e., an upward bus and a downward bus to realize high-speed packet switching.
FIG. 8 schematically shows an arrangement of a cell switch in the conventional packet switching system. The cell switch of FIG. 8 includes a unidirectional or simplex transmission bus 630, a time slot allocator 640 for controlling the simplex bus 630 in a time-divisional manner, access controllers 602 for transmitting data in the form of a cell onto the simplex transmission bus 630 in accordance with an instruction of the time slot allocator 640, and address filters 603 for monitoring the destination data field of the cell on the simplex bus 630 and for selectively receiving the cells which are directed to its own output port 620.
Serial data inputted through an input port 610-1 is converted at a serial-parallel converter 601 into parallel data, which is subjected to a time-divisional control at the access controller 602, and then transmitted onto the bus 630. Of the cell data transmitted onto the bus 630, the address filter 603 selectively receives data directed to its own port 620-1. The received parallel data is converted into serial data at a parallel-serial converter 604 and then outputted to the output port 620-1. In this manner, data is converted and transmitted to a desired destination. In the same manner, data from one of input ports 610-1 to 610-n is converted and transmitted to one of output ports 620-1 to 620-m.
FIG. 9 shows a conventional packet switching system in which two cell switches as shown in FIG. 8 are respectively used. When transmission is directed from one of terminal ports 801-1 to 801-7 to one of line ports 901-1 to 901-7, an upward bus 10 and an upward time-slot allocator 30 are used. For example, when the transmission is directed from the terminal port 801-1 to the line port 901-1, a cell switch, which comprises a serial-parallel converter 703, an access controller 704, an address filter 708, a buffer 709 and a parallel-serial converter 710, is operated. On the other hand, when the transmission is directed from one of the line ports 901-1 to 901-7 to one of the terminal ports 801-1 to 801-7, a downward bus 20 and a downward time-slot allocator 40 are used. For example, when the transmission is directed from the line port 901-1 to the terminal port 801-1, a cell switch, which comprises a serial-parallel converter 712, an access controller 711, an address filter 707, a buffer 706 and a parallel-serial converter 705, is operated.
Terminal interfaces 800-1 to 800-7 and line interfaces 900-1 to 900-7 are arranged on respective cards for each terminal port and each line port. In order to identify their own interfaces, addresses "0" to "D" are allocated to the interfaces (FIG. 13).
Referring to FIGS. 10 and 11, explanation will be made as to the flow of data in the upward direction, that is, from the terminal ports 801-1 to 801-7 to the line ports 901-1 to 907-7 in the cell switch of FIG. 9.
Referring to FIG. 10, when data is received from the terminal port 801 of a terminal interface 800, a cell assembler/disassembler 802 divides the received data into a plurality of 48-byte sub-data and attaches 5 bytes of a virtual communication path identifier (referred to as VCI, hereinafter) to each of the sub-data. Thus, cells each having 53 bytes are assembled. After assembling the cells, the cell assembler/disassembler 802 issues a cell transmission request to an access controller 805. The access controller 805, which has already received the address of its own terminal interface 800 from an address input line 813, receives the address of one of the terminal interfaces to which the transmission of the cell is permitted. When the address issued from the upward time slot allocator 30 coincides with the address of its own terminal interface 800, the access controller 805 issues a transmission approval signal to a serial-parallel converter 803. The serial-parallel converter 803, when receiving the transmission approval signal from the access controller 805, reads out the cell from a cell assembling/disassembling buffer (not shown) and converts the cell into parallel data. The cell outputted from the serial-parallel converter 803 is applied to a destination address (DA) attacher 804. The destination address attacher 804 extracts 2 bytes of a destination address (DA) from the identifier VCI of the cell, which is attached at the cell assembler/disassembler 802 and which is a path data indicating the address data of the line interface to be passed and the address of the terminal interface connected to another destination exchange, and attaches the destination address to the cell.
In the destination address attacher 804, there is provided a table showing correspondence between the VCIs and destination addresses (DAs) to be attached to the cell. The table corresponds the identifier VCI0 to the destination address DA0, . . . , VCIi to DAi, . . . , and VCIn to DAn. After the destination address is attached and thus the assembling of the 55-byte cell is completed, the terminal interface 800 transmits the cell onto the upward bus 10.
Referring to FIG. 11, explanation will be made as to subsequent upward flow of the cell data. Since all of the line interfaces are connected to the upward bus 10, a line interface 900 can receive all cells transmitted onto the upward bus 10. When the line interface 900 receives the cell from the bus 10, the destination address (DA) of the received cell is sent to an address filter 910 (more specifically, through an destination address (DA) reader 911 to a comparator 912, both provided in the address filter 910). The comparator 912 compares the destination address (DA) of the received cell with its own address already received from an address input line 913. When the destination address of a cell coincides with its own address, the comparator 912 sends the cell to a buffer 908. A destination address (DA) header deleter 909 removes the destination address (DA) from the cell thus received and stores it in the buffer 908. Thereafter, the cell read out from the buffer 908 is converted at a parallel-serial converter 907 into serial data and then output to a line port 901 through a line input/output interface 902.
Explanation will next be made on the downward transmission, i. e., from the line ports to the terminal ports. Referring to FIG. 11, when receiving data corresponding to one cell from the line 901, the line input/output interface 902 issues to an access controller 905 a cell transmission request to the downward bus 20. To the access controller 905, the address of the line interface is also applied to which data transmission is permitted from the downward time slot controller 40. The address of its own line interface 900 has already been received from the address input line 913. A comparator 906 of an access controller 905 compares the address issued from the downward time slot controller 40 with the address of its own line interface 900. When the both addresses coincide, the comparator 905 issues a transmission approval signal to the serial-parallel converter 903. The serial-parallel converter 903, when receiving the transmission approval signal, reads out the cell from a line interface buffer (not shown) and converts it into parallel data. The converted cell data is sent from the serial-parallel converter 903 to a destination address (DA) attacher 904. The destination address attacher 904 refers to the cell identifier (VCI) attached to the received cell and attaches the address of the terminal interface to which the cell is to be transmitted, i.e., the destination address DAi (2 bytes) to the cell. After attaching the destination address DAi to the cell so as to complete the assembling of a 55-byte cell at the destination address attacher 904, the line interface 900 transmits the cell to the downward bus 20.
Referring back to FIG. 10, the explanation of subsequent downward flow of the cell data will be made. The downward bus 20 is connected to all the terminal interfaces so that the terminal interface 800 can receive all cells transmitted onto the downward bus 20. Accordingly, when the terminal interface 800 receives the cell from the bus 20, the destination address (DA) of the received cell is sent to an address filter 810 (more specifically, through an destination address (DA) reader 811 to a comparator 812, both provided in the address filter 810). The comparator 812 compares the destination address (DA) of the received cell with its own address already received from an address input line 813. When these addresses coincide with each other, the comparator 812 sends the cell to a buffer 808. A destination address (DA) header deleter 809 removes the destination address (DA) from the cell thus received and stores it in the buffer 808. Thereafter, the cell read out from the buffer 808 is converted at a parallel-serial converter 807 into serial data, converted at the cell assembler/disassembler 802 into data of terminal format, and then output to the terminal port 801.
The switching/transmission of cells between the terminals and lines has been explained above. Referring back to FIG. 9, in actual applications, there are other cell switching/transmission methods such as extension communication in which a cell received from one terminal port is transferred to another terminal port, e.g., from the terminal port 801-1 to the terminal port 801-2, switching relay in which a cell received from one line port is transferred to another line port, e.g., from the line port 901-1 to the line port 901-2, and loopback in which a received cell from a terminal or line port is transferred back to itself.
With the exchange having the conventional cell switches, the loopback communication is realized by using a line- or terminal-side loopback unit 1000 or 1100 (FIG. 9).
Explanation will be made below as to the switching/transmission with use of the line- and terminal-side loopback units 1000 and 1100. First, the switching relay using the line-side cell loopback unit 1000 and the line-side loopback operation will be explained by referring to FIG. 12. The illustrated line-side cell loopback unit 1000 receives a cell from the downward bus 20, attaches, at a destination address attacher 1004, a destination address (DA) to the received cell, and then transmits the address-attached cell onto the upward bus 10 from the destination address attacher 1004. In other words, the line-side cell loopback unit 1000 has a function of switching to the upward bus 10 in such a manner that a cell transmitted from a line interface can be received again by the same line interface. Accordingly, switching relay between lines i and j is realized in the following manner. First, the destination address attacher of the line interface i connected to the line i is previously arranged so that a destination address (DA) is set to be "E" with respect to an identifier (VCIj), whereby a cell designated by the identifier (VCIj) indicative of switching relay to the line j is transferred to the line-side cell loopback unit 1000, wherein the symbol "E" denotes the address of the line-side cell loopback unit 1000. Similarly, the line-side cell loopback unit 1000 is previously set so that a destination address (DAj) to be transferred to the line interface j connected to the line j is given with respect to the identifier (VCIj).
When the destination address attacher is set in such a manner as described above, the cell received from the line i is switched and relayed to the line j. On the other hand, when a cell received from the line j is switching-relayed to the line i, the line interface j is previously designed so as to set the destination address DA to be "E" for an identifier (VCIi), while the line-side cell loopback unit 1000 is designed so as to set an destination address (DAi) for the identifier (VCIi).
The line-side loopback can be similarly realized by setting a table in the destination address attacher. For example, when the loopback is carried out with respect to the line i, the line interface i is designed so as to set the destination address (DA) to be "E" for an identifier (VCIib), while the line-side cell loopback unit 1000 is designed so as to set the destination address (DAi) for the identifier (VCIib).
Now, the switching relay and the line-side loopback operation have been explained in connection with the use of the line-side cell loopback unit as an example. Similarly, the extension communication and the terminal-side loopback can be carried out with use of the terminal-side cell loopback unit.
FIG. 13 is a schematic view of a conventional packet switching system. As shown in FIG. 13, the packet switching system comprises two upward and downward cell switches. In the back plane, there are provided a total of 44 lines, that is, two sets of 4 address bus lines, two sets of 2 clock signal lines, and two sets of 16 data bus lines. Further, two cards of terminal- and line-side loopback units for extension communication, switching relay or loopback are mounted.
Since the conventional system comprises the 2 upward and downward cell switches, the two sets of address buses, clock signals and data buses must be provided in the back plane of the cell switches. In addition, for the purpose of realizing such communication as the extension communication, switching relay or loopback, the system requires dedicated cards (hardware). As a result, the conventional system has had such a problem that the system has become complicated and requires large-scale hardware.